The present invention relates generally to clock and data recovery (CDR) circuits, and more specifically to reducing the latency associated with a CDR circuit.
Clock and data recovery (CDR) operations are performed in many communication circuits. Digital communication receivers sample an analog waveform and then detect the sampled data. The phase of the analog waveform is typically unknown and there may be a frequency offset between the frequency at which the original data was transmitted and the nominal receiver sampling clock frequency. The CDR circuit is used to sample an analog waveform such that when the sampled waveform is passed through a data detector, the data is recovered properly despite the fact that the phase and frequency of the transmitted signal is unknown.
FIG. 1 shows a prior art serializer/deserializer (also referred to as a Serdes) communication macrocell 100. The macrocell 100 includes multiple channels, such as a first channel (i.e., channel 0) 104, a second channel (i.e., channel 1) 106, and a (P−1)th channel (i.e., channel P) 108. Each channel performs its own CDR function. A common reference clock generation circuit 110 provides a reference clock signal (REFCLK) 112 to each of the channels 104-108, which is used to sample a respective analog waveform 114a, 114b, 114c. The CDR circuit adjusts the phase and frequency of the reference clock 112 to produce a modified clock signal (also referred to as a recovered sampling clock signal) 118a, 118b, 118c. The modified clock signal 118a, 118b, 118c can sample the respective analog waveform 114a, 114b, 114c to allow proper data detection. When a data detector 122a, 122b, 122c reaches its steady state, then the respective analog signal 114a, 114b, 114c is sampled correctly and the corresponding data detector 122a, 122b, 122c transmits recovered/retimed data 126a, 126b, 126c as its output.
Each of the data detectors 122a, 122b, 122c can be a decision device based on an amplitude threshold or a more complicated detector such as a sequence detector. As a CDR circuit is replicated multiple times, area and power efficiency of the CDR hardware are often critical.
FIG. 2 shows a block diagram of a traditional analog CDR circuit 200 using a VCO. The CDR circuit 200 receives an analog signal 202 as input. The CDR circuit 200 includes a data detector 204, phase detector 208, analog loop filter 212, and one or more circuits to change the sampling phase with which the data detector input is sampled. The data detector 204 produces recovered/retimed data 214.
One circuit commonly used to change the sampling phase is a voltage controlled oscillator (VCO) 216. The output of the VCO 216 is a recovered sampling clock 220. As the CDR circuit 200 is a closed-loop system, the recovered sampling clock 220 is used to adjust the sampling of the analog signal 202. A VCO 216 changes its output clock frequency continually to accommodate any difference in phase and frequency with respect to the received analog signal 202.
One drawback of the CDR circuit 200 is that the analog loop filter 212 consumes a lot of area on the integrated circuit chip on which the CDR circuit 200 is designed. For example, the analog loop filter 212 is built with many chips or is built with particular chips that consume a large amount of surface area on the integrated circuit chip.
FIG. 3 shows a CDR circuit having another circuit commonly used to change the sampling phase—a phase selection circuit (PSC) 302. A PSC may be implemented as a multiplexer, a voltage controlled delay line (VCDL), or a current controlled delay line (CCDL). A PSC changes its output phase continually to accommodate any difference in phase and frequency with respect to the received analog signal.
The circuit 300 includes a data detector 303, a phase detector 304, and a traditional digital loop filter 305 that can be used in conjunction with PSC 302. The PSC 302 continually adjusts the phase of reference clock (i.e., REFCLK) 312 to effectively modify its phase and/or frequency to produce a recovered sampling clock 316. The recovered sampling clock 316 is used to sample analog signal 324.
Digital loop filters, such as digital loop filter 305, often consume less chip area then an analog loop filter. Digital loop filters, however, typically introduce more latency into the CDR circuit relative to their analog counterpart.
Therefore, there remains a need to retain the circuit area benefit achieved from a digital loop filter while reducing the latency introduced into a CDR circuit by the digital loop filter.